High-density integrated thin film capacitors utilize a patented multi-layer production process to deliver custom capacitor arrays for size-critical applications. A single chip can be designed to include multiple high-density; capacitors with integrated routing and fine-pitch I/O pads, saving board space and eliminating the need for surface-mount capacitor placements. Flexible I/O placement enables simple die stacking, flip chip or wire bond packaging options.Relative to discrete capacitors integrated capacitors offer superior performance advantages including excellent matching characteristics, stability over temperature, time and applied voltage, and the ability to locate high quality capacitance directly at critical nodes of the system thereby minimizing parasitic effects.

SiPArray and 3D Chip Stacking
Technology Provides Dramatic Size & Weight Reduction Benefits

SiPArray technology enables extreme miniaturization in 3D multi-chip packages. In typical assemblies, SiPArray offers 97% reduction in package size as compared to traditional SMT (surface mount technologies).

Application: SiPArray Integrated Passive Capacitor Chips used in a miniaturized 3D Chip Stacking Architecture (MCM)

The following case study illustrates the application of SiPArray Integrated Capacitor Chips (CAP 1 and CAP 2) into a 3D chip stacking architecture (hearing aid application) to achieve an extremely miniaturized S-CSP (Stacked Chip Scale Package).

Figures 3, 4 and 5 below illustrate a sample application involving the flip-chip placement of an analog-to-digital converter IC and EEPROM, onto a SiPArray IC(CAP 1), which is then mounted on top of a DSP device and wire-bonded to the main substrate. A second SiPArray (CAP2)is directly flip-chipped onto the main substrate providing additional filter and decoupling capacitance without the need for discrete bulk capacitors, minimizing system size and assembly costs.

Beyond providing an integrated capacitor network the SiPArray capacitor chips also function as an integral part of the overall mechanical structure of these S-CSP architectures, providing additional high density signal routing planes and physical interposer layers.

SiPArray™ Technical Specifications

For more information on custom designs and further passive integration possibilities please contact our IPD group @ aditya.jain@onsemi.com or call +1 (602) 244-3501